The key benefit in Channel Link II/III SerDes is their operation with smaller interfaces. By serializing the data and clock into a single high speed lane, the data can be carried over fewer cables and smaller interconnects. Smaller interconnects are easier to layout, weigh less, offer better high frequency performance, and lower the overall system cost. 2nd & 3rd generation Channel Link SerDes bring many new other features such as: an embedded clock scheme that removes the need for critical ps level matching between clock and data, integrated signal conditioning features extend the reach over low cost cable and flexibility on interface (LVCMOS vs. LVDS) which allows the designer the ability to connect to the host device.