GaN Power Devices

2. Select the Right GaN Device

Use the Following Tools to Select Your Device

Read this article to learn why you shouldn’t use RDS(on) to select and compare devices in switching power converters.

Use GaN FET Thermal Calculator to Simulate Your Solution

Once you have identified a few devices that work for your application, you can evaluate how they will work in your thermal environment with the GaN FET Thermal Calculator. It allows the optimization of the thermal solution once the losses have been determined.

Consider Packaging Options

EPC’s GaN FETs and ICs are offered in chip-scale packaging (CSP) and Plastic Quad Flat No-Lead (PQFN) packaging. The choice between CSP and PQFN depends on the specific requirements of the application. CSP is well-suited for size-constrained, high-power density applications. PQFN packages offer a balance between high performance and ease of manufacturing.

Consider Reliability

Product reliability is a critical consideration when selecting the right device.  eGaN® devices have been in volume production since March 2010 and have demonstrated very high reliability in both laboratory testing and high-volume customer applications with a remarkable field reliability record.

EPC has an extensive test-to-fail reliability program and regularly publishes the results of these studies.  For the latest reliability reports please visit the reliability resources page.

Key Reliability Topics Covered:

• Physics-based lifetime models for gate stress and drain stress
• Safe operating area
• Short-circuit robustness
• Mechanical stress
• Thermo-mechanical stress
• Test-to-fail methodology to accurately predict application-specific device lifetime

3. Drivers and Controllers

Selecting the right GaN driver or controller is critical to achieving robust, high-performance designs in GaN power conversion systems. In this section of EPC’s GaN First Time Right™️ design framework, you’ll find detailed guidance on compatible gate drivers, controller architectures (buck, boost, half-bridge, synchronous rectification), and selection criteria such as dead-time, propagation delay, and gate protection. Each recommendation is backed by tested reference designs and rich application data to help you integrate drivers and controllers that maximize efficiency, reliability, and speed in GaN-based systems.

Learn how to use GaN FETs with controllers and gate drivers designed for silicon MOSFETs.

In some situations, a designer might want to use a generic gate driver or controller. This is often possible (as an example in EPC9153 Buck Converter) but there are a few points that need to be investigated, including:

1. High-side bootstrap voltage “clamp” - for low-side FET reverse current conduction (reverse conduction voltage is as high as 2.5 V which can charge the bootstrap capacitor to over 7 V) for bootstrap power supply-driven half-bridge drivers.
2. EPC eGaN FETs should be driven with a turn on voltage of 5.0 to 5.5 V, but no lower than 4.5 V, and a turn off voltage of 0 V. Therefore, the driver under voltage lockout (UVLO) should be checked and is recommended to be in the range 3.6 V for disable and 4.0 V for enable.
3. Since GaN devices can switch very fast, the gate driver should be able to withstand these high dv/dt; a capability > 100 V/ns is recommended.
4. Minimum deadtime should be low enough to minimize deadtime losses, ideally in the 20-40ns range: Dead-Time Optimization for Maximum Efficiency
5. A small, low-cost Schottky diode in parallel with the lower FET may be needed. See board EPC9153 Buck Converter for an example.

Identify a monolithic GaN integrated circuit to meet your design requirements.

4. Schematic and Layout

Find and Download Schematic to Start Designing

EPC publishes the schematic for all evaluation boards to allow for easy copy and paste of designs containing all critical components and a layout that supports optimal switching performance. Select the evaluation board of interest from our growing list of designs and find the schematic along with bill of materials and gerber files to get your design started.

Schematic Symbol for GaN FETs

EPC uses the standard MOSFET symbol for GaN FETs to make it easier for designers. Enhancement‐mode GaN transistors do not have a p–n body diode as in a silicon power MOSFET, but they do conduct in the reverse direction in a way that is like the diode in a power MOSFET. However, because there are no minority carriers involved in conduction in an enhancement-mode GaN transistor, there is no reverse recovery charge. Q_RR is zero, which is a significant additional advantage compared with power MOSFETs.

The recommended design for Optimizing PCB Layout with eGaN FETs (WP010) utilizes the first inner layer as a power loop return path. This return path is located directly beneath the top layer’s power loop allowing for the smallest physical loop size. Variations of this concept can be implemented by placing the bus capacitors either next to the high-side device, next to the low-side device, or between the low and high-side devices, but in all cases, the loop is closed in the inner layer right beneath the devices. A similar concept is also used for the gate loop, with the return gate loop located directly under the ON and OFF gate resistors.

Furthermore, to minimize the common source inductance between power and gate loops, the power and gate loops are laid out perpendicular to each other, and a via next to the source pad closest to the gate pad is used as Kelvin connection for the gate driver return path.

Guidelines for Effective Parallelling of GaN Devices

For higher-power applications, it may be necessary to place multiple transistors in parallel and have them behave as a single device. GaN devices parallel extremely well because:

• The RDS(ON) has a positive temperature coefficient, so in the ON-state the current will self-balance based on each device temperature
• The QG of GaN FET is much lower than comparable Si MOSFET, therefore the requirements and the losses in the gate driver are minimized
• The VTH of GaN FET is very stable over temperature, as compared to a strongly negative temperature coefficient for Si MOSFET, this allows good current sharing also during switching events

However, to ensure good current sharing in dynamic conditions, it is also important to pay attention to the layout:

• Individual gate resistors should be used for each GaN FET, placed near the FETs
• All parasitic inductances in the layout should be kept as similar as possible for each paralleled device, both for the power loop and gate loop
• For high-performance applications, we recommend a layout technique of paralleling half-bridges instead of single devices: Paralleling High Speed GaN Transistors (AN020). An example of implementation is shown in EPC90135: 100 V, 45 A Parallel Evaluation Board
• For a simpler approach of a parallel layout with 4 devices in parallel we recommend the technique used in the motor drive reference design EPC9186: 150 ARMS, wide input voltage 3-Phase BLDC Motor Drive Inverter

An example of a parallel layout with 4 devices in parallel is the EPC90135: 100 V, 45 A Parallel Evaluation Board

Best Practices for eGaN FET Footprint Design

Many EPC parts are offered in a Wafer Level Chip Scale Package (WLCSP) using a fine pitch down to 400 µm. This means a proper PCB footprint design is essential for consistent and reliable assembly of the GaN device. Detailed recommendations can be found here How2AppNote008 - Designing PCB Footprint eGaN FETs ICs, and recommended land patterns (solder mask opening) and stencil designs are provided in each datasheet. EPC also provides an Altium Library with all the EPC footprints. The video Footprint Design – PCB CAD System Independent guides customers through a CAD-independent detailed explanation of how to create their own footprints.

EPC recommends the use of a Solder Mask Defined (SMD) pad over a Non-Solder Mask Defined (NSMD) pad for two reasons:

• A Solder Mask Defined (SMD) footprint yields lower inductance and improves alignment during reflow.
• A Non-Solder Mask Defined (NSMD) footprint has a higher probability of die misalignment during reflow, which can reduce the effective copper contact area thereby degrading the solder joint and current carrying capability of the device.

EPC recommended silkscreen design should include:

• 4 corner registration marks outlining the part shape.
• Lines drawn with an open narrow dash: a solid line rectangle surrounding the part, thus preventing flux from flowing away from the die during the reflow process, can create a flux dam and trap flux under the part.
• Unique Pin one identifier.

If you would like the EPC team to review your design once the schematic and layout are done, please submit request to info@epc-co.com

5. Loss calculation

Simulate Electrical Performance with GaN Devices

The ability to simulate GaN devices without practically using them is an extremely important step in the design process. For more detailed electrical simulations, EPC utilizes a hybrid of physics-based and phenomenological functions to achieve a compact spice model with acceptable simulation and convergence characteristics, including temperature effects for conductivity and threshold parameters. These can be found on the EPC Device Models page, while the Circuit Simulation Using EPC Device Models provides an in-depth look at these models. Supported model formats include P-SPICE, LTSPICE, TSPICE, SIMPLIS/SIMetrix, and Spectre. Also included on the Models page are STEP, Thermal Models, and the EPC Altium Library.

6. Thermal Management

Maximize Power with Advanced Heatsink Designs

It is important to note that EPC GaN FETs can take advantage of dual-sided cooling to maximize their heat dissipation capabilities in high-power density designs. This is covered in detail in How2AppNote012 - How to Get More Power Out of an eGaN Converter.

Optimize Cooling with Premium Thermal Interface Materials

Thermal interface materials (TIM) are a critical part of the cooling system when using top sided cooling. Since GaN devices are very small, effective cooling relies on the heat-spreading effect of the heatsink, however, the TIM layer does not benefit from this. Because of its small area, the TIM layer ends up being a significant contributor to the overall Rth,J-A, and therefore the use of high thermal conductivity materials is very beneficial. The TIM layer also has a very important second role: to electrically isolate the GaN devices from the heatsink since the top of EPC GaN FETs are connected to source potential.

EPC has gathered some information on TIM materials to help designer in their search:

7. Assembly

Visual Characterization

When starting a new production process, it is common to set up incoming visual inspections. To simplify this process, detailed descriptions of the EPC FETs and ICs physical characteristics including the visual criteria all devices must meet before they are released for shipment to customers are given in the Enhancement Mode GaN FETs and ICs Visual Characterization Guide

8. Measurement

GaN FETs can switch much faster than Si MOSFETs.

Switch node comparison at 15A (48 Vin, 12 Vout buck converter)

This can cause challenges during the measurement phase.

See AN023 Accurately Measuring High-Speed GaN Transistors for more details

Tips and tricks

GaN FETs high performance emphasizes the need for good measurement techniques for high-speed circuits.

1. The ground loop should be minimized by utilizing a spring clip
2. Probing location should be kept as close as possible to the device being tested

Bandwidth requirements

If scopes or probes with insufficient bandwidth are used, then actual waveforms of a typical converter cannot be measured accurately. A 500MHz bandwidth is recommended for typical converters, and at least 1 GHz for some specific applications like LIDAR.

Effect of probe/system bandwidth on captured waveform (EPC9080 based board)

Differential probes

Of particular interest is the measurement of the high side gate in a typical half-bridge configuration. On top of the previous requirement in terms of bandwidth and measurement setup, this measurement presents additional requirements: 

1. Galvanic isolation: although the math channels can be used to reconstruct the high side gate, this method is susceptible to noise and mismatch between the two probes. A differential probe is recommended
2. Large common mode rejection ratio (CMMR
3. Common mode voltage rating > input voltage (Buck) or output voltage (Boost
4. Large input impedance, preferably > 10 MΩ || < 2pF 

Test equipment manufacturers have developed high performance differential probes suitable for this: for example Tektronix IsoVu, LeCroy DL-ISO, and PMK Firefly probes.

Double pulse measurements

This measurement method is commonly used to directly measure switching losses of semiconductor devices by using the math function of a scope to multiply the instantaneous voltage and current waveforms and then integrating them. The previous methods can be applied to measure the voltage, however measuring the current has these additional challenges:

• Bandwidth requirement: active current sensors struggle with the accuracy and bandwidth required, so current shunts are still the preferred method
• Current shunts require interrupting the power loop and inserting the sensor. The increase in power loop inductance can significantly change the measurement results

For these reasons EPC does not recommend double pulse testing, but rather utilizing Spice models (and a calibrated model if more accuracy is needed): EPC Device Models

Test equipment manufacturers are working on this topic, for example see the article Accurate Characterization of Low-Voltage, Small-Form–Factor GaN FETs.