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MAX96716 Dual GMSL2 to CSI-2 Deserializer
Analog Devices deserializers can transmit data over low-cost 50 Ω coax or 100 Ω STP cables that meet GMSL2 channel specification

Analog Devices MAX96716 deserializers convert dual GMSL2 serial inputs to a MIPI CSI-2 output. They also transmit and receive control-channel data, enabling transmission of forward-path video and bidirectional control data. The GMSL2 link operates at a fixed rate of 6 Gbps or 3 Gbps in the forward direction and 187.5 Mbps in the reverse direction. The GMSL inputs operate independently, allowing video with different timing and resolution to be received on each input. Video data from both inputs can be aggregated for output on a single CSI-2 port or replicated on a second port for redundant processing. The device and connected serializer are programmed through I²C or UART. Operation is specified over the automotive temperature range of -40°C to +105°C, and the device is AEC-Q100 qualified. Data may be transmitted over low-cost 50 Ω coax or 100 Ω STP cables that meet the GMSL2 channel specification.

MAX96716 evaluation kits (EV kits) provide a reliable platform for evaluating MAX96716 ICs through the use of standard FAKRA coaxial cables or an HMTD cable. The EV kit includes a simple-to-use Windows 7/Windows 10-compatible graphical user interface (GUI) for exercising device features. For complete GMSL-2 evaluation using a standard FAKRA coax cable or HMTD cable, order the MAX96716 COAX/STP EV kit along with a companion serializer board.

  • Full-duplex capability over a single coax or STP cable
    • 3 Gbps or 6 Gbps forward-link rates
    • 187.5 Mbps reverse-link rate
  • Dual 4-lane D-PHY or dual 2-lane C-PHY MIPI CSI-2 v1.3 output ports
    • Aggregation and replication functions
    • 16 virtual channel support
    • Supports RAW8/10/12/14/16/20, RGB565/666/888, YUV422 8-bit/10-bit, user-defined, and generic long packet data types
  • Advanced MIPI D-PHY v1.2 transmitters
    • 80 Mbps to 2.5 Gbps per lane
  • Advanced MIPI C-PHY v1.0 transmitters
    • 182 Mbps to 4.56 Gbps per lane
  • Reference-over-reverse (RoR) channel supports crystal-free operation
  • ASIL-relevant functional safety features
    • ASIL-B compliant
    • End-to-end data integrity through cyclic redundancy check (CRC) in tunnel mode
    • R-S FEC for protection of forward video and control channel data
    • 16-bit CRC protection of side-channel data (I²C, UART, SPI, and GPIO) with retransmission upon error detection
    • 32-bit CRC protection of video line data
  • Forward- and reverse-channel pseudo-random binary sequence (PRBS) for BER testing of serial link
  • Continuous link margin monitoring and optimization
    • Continuous adaptive equalization
    • Forward- and reverse-channel eye-opening monitor for continuous link margin diagnosis
  • Concurrent side-channel for device configuration and communication with peripherals
    • I²C/UART, pass-through I²C/UART, SPI, GPIO, and register-programmable GPIO
    • Four hardware-programmable device addresses
  • 48-lead 7 mm x 7 mm TQFN side-wettable package with a 0.5 mm pitch